© 2026 SimplEx Micro

NEWS AND INSIGHTS

RISC-V News and Insights

Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High Performance  RISC-V CPUs
September 1st, 2025
Condor Computing’s Cuzco, a High Perf RISC-V Design
at Hot Chip 2025
RISC-V Startup Condor Computing’s Cuzco Core Takes Flight
August 25th, 2025
Rethink Scoreboards to Supercharge AI-Era CPUs
July 1st, 2025
Speculative Execution: Rethinking the Approach to CPU Scheduling
May 7th, 2025
Predictive Load Handling: Solving a Quiet Bottleneck in Modern DSPs
April 17th, 2025
Even HBM Isn’t Fast Enough All the Time
April 7th, 2025
CEO Interview with Dr. Thang Tran of Simplex Micro
March 18th, 2025
With MTIA V2 Chip, Meta Can Do AI Inference, But Not Training
The Next-Generation Meta Training and Inference Accelerator
MTIA: Meta’s First Generation of AI Accelerators
APRIL 10th, 2024
Tutorial: RISC-V Vector Extension Demystified – 2020 RISC-V Summit
Next-Generation Vector Processor Design I
Next-Generation Vector Processor Design II
Next-Generation Vector Processor Design III
Next-Generation Vector Processor Design IV
september 21st, 2023
–  This collection of online lectures was led by Thang Tran and provide over 6 hours of insight into vector processor design
MTIA: First Generation Silicon Targeting Meta’s Recommendation Systems
June 23rd, 2023
– The 512-bit OoO RISC-V vector processor was architected and designed by Thang Tran
Naveed Sherwani on Meta’s MTIA
may 20th, 2023
MTIA v1: Meta’s first-generation AI inference accelerator
MAY 18TH, 2023

© 2026 SimplEx Micro